1. Field of the Invention
The invention relates to a simple demodulator for a proposed wireless standard. More particularly, the invention relates to a simplified detector for nine bit even parity QPSK symbols.
2. Background
The IEEE 802.16 Broadband Wireless Access Working Group has a proposal entitled “PHY layer proposal for BWA,” IEEE 802.16.1pc dated Feb. 25, 2000. A required modulation format in this proposal is QPSK (Quadrature Phase Shift Keying). In Section 6.2.2.1.1 of the proposed standard, forward error correction employing a Reed Solomon (RS) code over Galois Field GF(256) is proposed. The RS encoder encodes k user bytes and appends r redundant bytes to form systematic codewords, each consisting of n=k+r bytes. A well-known property of RS codes is an errors-only RS decoder can correct any combination of t erroneous bytes provided that 2t<=r. It is possible to extend the power of the RS code by utilising a demodulator which marks bytes suspected of being in error with an erasure flag. In this case, an errors-and-erasures RS decoder can correct any combination of t erroneous unflagged bytes and v flagged bytes provided that 2t+v<=r. Three choices for k and r are proposed, as shown in Table 1.
TABLE 1FEC ParametersPortionkrControl and data transport12810Registration146Contention54
In section 6.2.2.1.2 of the proposed standard it is proposed that each eight-bit byte of the RS code is appended with a single parity bit. In a system which uses these parity bits, a total of nine bit symbols are transmitted over the channel for each byte.
QPSK is detected by decomposing the received waveform into I and Q (In-phase and Quadrature) signals, each of which is match-filtered and synchronously sampled. With a perfect estimate of the carrier phase, there is no crosstalk or interference between the signals. The simple threshold detector can be used on each of the sampled outputs of the matched filters.
As a baseline for comparison, the error performance of a system transmitting 8-bit symbols without the parity bits of section 6.2.2.1.2 of the proposed standards can be characterised (before and after errors-only RS decoding) as a function of a Signal-to-Noise Ratio (SNR) of the received signal.
By monitoring the detected bits of the nine bit symbols in a system using the parity bits of section 6.2.2.1.2, an erasure flag can be generated wherever the parity of the detected symbols is incorrect. An errors-and-erasure RS decoder using these flags offers improved performance over the baseline system. This improved performance requires extra complexity in the receiver, since a high throughput errors-and-erasure RS decoder is typically twice the complexity of an errors-only decoder.
It is desirable to have a modulation scheme which achieves similar or better performance without the need for extra complexity in the RS decoder.